The present invention relates generally to integrated circuits, and more specifically to the masking of data being written to an integrated circuit such as a memory device.
A semiconductor integrated circuit device, such as a dynamic random access memory (DRAM), includes a die or chip, which is a small piece of semiconductor material in which electronic circuitry (i.e., integrated circuit) is formed. The chip is physically and electrically attached to a chip package, which is a protective container, such as a plastic dual-in-line package (DIP) or printed circuit board to which the chip is coupled. The chip is typically electrically coupled the chip package by forming electrical connections between bonding pads on the chip and leads or pins on the chip package.
As the functionality of integrated circuit devices increases, the complexity of the electronic circuitry typically increases along with the required number of pins on the chip package required to support this increased functionality. For example, as the storage capacity of a DRAM increases, more address pins are required to access the data stored in the DRAM. Each segment of data is stored in a unique address in the DRAM, and as the amount of data and thereby the number of segments of data increases, the number of unique addresses must also increase, which requires more address pins. As the number of pins increases, the cost of the DRAM or other integrated circuit device also increases due to the physical formation of additional pins on the chip package as well as the increased manufacturing and testing costs due to the interconnection of more bonding pads on the chip and pins on the chip package.
In a typical application, a plurality of DRAMs are mounted on a circuit board to form a memory module. Each DRAM receives address and control signals through address and control terminals on the circuit board, and has a data bus coupled to a corresponding data terminals on the circuit board. Typically, the memory module has a data bus that is M bits wide, where M is an integer multiple of N, which is the width of the data bus of each DRAM. Each DRAM on the module provides N of the M bits in response to common address and control signals applied to all DRAMs on the module. For example, a typical memory module includes 8 DRAMs each having an 8 bit wide data bus to form a 64 bit wide data bus on the memory module. Another typical memory module includes 9 DRAMs, each having an 8 bit wide data bus to form a 72 bit wide data bus on the memory module with 8 bits that function as error checking and correction bits. As with individual DRAMs, as the number of terminals on the memory module increases, the cost of the memory module increases due to the physical formation of more terminals, increased complexity in informing electrical interconnectors on the circuit board, and increased manufacturing and test costs.
FIG. 1 is a simplified block diagram of a DRAM 100 including an address decoder 102 that receives address bits A0-AX on an address bus ADDR and decodes these address bits and applies decoded address signals 104 to a memory-cell array 106. The memory-cell array 106 includes a plurality of memory cells (not shown) arranged in rows and columns, each memory cell storing a bit of data. The data stored in the memory cells is accessed in response to the decoded address signals 104 from the address decoder 102. A read/write circuit 108 is coupled to the memory-cell array 106 through an internal data path 110 and is coupled to an external data bus DATA of the DRAM 100. In the example of FIG. 1, the data bus DATA includes 8 external terminals over which data bits DQ0-7 are transferred to and from the DRAM 100, and also includes a terminal over which a data masking signal DM is received during write operations. The read/write circuit 108 masks data bits DQ0-7 in response to the data masking signal DM, as will be described a more detail below.
The data bus DATA can include more of fewer terminals, such as 32, 16, or 4 terminals to transfer a corresponding number of data bits. The DRAM 100 also includes control logic 112 that receives a plurality of control signals applied on an external control bus CONT. In response to the control signals, the control logic 112 generates a plurality of control and timing signals 114 to control the timing and operation of the address decoder 102, memory-cell array 106, and read/write circuit 108 during operation of the DRAM 100.
In operation, an external circuit (not shown) such as a memory controller applies address, control, and data signals to the DRAM 100 over the address bus ADDR, control bus CONT, and data bus DATA, respectively, to control the operation of the DRAM. During read operations, the external circuit applies a read command to the DRAM 100 in the form of appropriate address signals on the address bus ADDR and control signals on the control bus CONT. In response to the applied address signals, the address decoder 102 accesses addressed memory cells in the memory-cell array 106 and applies the read data stored in the addressed memory cells over the internal data path 110 to the read/write circuit 108 which, in turn, places the read data on the data bus DATA as read data bits DQ0-7. The control logic 112 generates the appropriate control and timing signals 114 to control the address decoder 102, memory-cell array 106, and read/write circuit 108 during the read operation.
During write operations, the external circuit applies a write command to the DRAM 100 in the form of appropriate address signals and control signals on the ADDR and CONT buses, respectively, and also applies write data bits DQ0-7 on the data bus DATA. Once again, in response to the applied address signals, the address decoder 102 accesses the addressed memory cells in the memory-cell array 106. The read/write circuit 108 transfers the applied write data bits DQ0-7 over the internal data path 110 and into the addressed memory cells in the memory-cell array 106. The control logic 112 operates during write operations to generate the appropriate control and timing signals 114 to control the address decoder 102, memory-cell array 106, and read/write circuit 108.
Also during write operations, the external circuit may activate the data masking signal DM to mask the write data bits DQ0-7. When the data masking signal DM is activated, the data bits DQ0-7 are not written into or are xe2x80x9cmaskedxe2x80x9d from the corresponding addressed memory cells in the array 106, as will be appreciated by those skilled in the art. When the data masking signal DM is deactivated, the write data bits DQ0-7 are written into the corresponding addressed memory cells in array 106.
The masking of data being written to the DRAM 100 using the data masking signal DM is used frequently in some applications while being used seldom if at all in other applications. For example, 8 or 9 of the DRAMs 100 are many times combined to form a memory module having a 64 or 72 bit wide data bus as previously described. Each DRAM 100 on the memory module receives a corresponding DM signal from an external controller, such as a memory controller or processor, which the controller selectively activates to mask selected bytes (i.e., 8 bits) of write data on the data bus. When the memory module is being used in graphics applications such as on a video card in a personal computer, the external controller typically frequently activates the data masking signals DM to mask selected bytes of write data on the data bus. The data masking functionality of the DRAMs 100 is particularly useful in such graphics applications where, for example, a background color may not be changing and thus the data corresponding to the background color will be masked while other data is changing and is thus not masked. In other applications, such as when the memory module is being used as part of system memory in a personal computer, the masking of write data via the data masking signals DM is seldom done.
In each DRAM 100, the data masking signal DM requires a separate external pin, and, as previously mentioned, such external pins increase the cost of the memory module as well as the cost of individual DRAMs 100. Moreover, the numbers of the memory modules containing such DRAMs 100 that will be used as system memory in personal computers is greater than the number of memory modules that will be used in graphics applications. As a result, the data masking signals DM of the DRAMs 100 will not be used in most applications but still consume pins on the memory module. The data masking signals DM require 8 or 9 external pins on the memory module that could otherwise be used for other functions or eliminated to reduce the cost of the memory module, at least in applications where data masking is not required. It should also be noted that the required number of data masking signals increases as the width of the data bus of the memory modules increases, at least if masking at the byte level is to be maintained.
There is a need for reducing the number of pins and cost of memory modules and of DRAMs forming such memory modules, and for reducing the frequency of applications where pins on the memory module and DRAMs go unutilized.
According to one aspect of the present invention, a method of masking data being written to a memory device having a data bus includes applying masking data on the data bus, storing the masking data in the memory device, applying write data on the data bus, storing the write data in the memory device, and applying the stored masking data to mask the stored write data.
According to another aspect of the present invention, a read/write circuit receives data words and data masking words applied on a data bus and receives read data from a memory-cell array. The read/write circuit operates during a read mode to apply read data received from the array on the data bus. During a write-partial mode, the read/write circuit stores at least one data masking word and at least one data word applied on the data bus, and applies each data masking word to mask each data word, and thereafter applies each masked data word to the memory-cell array.